MB86831 Datasheet, PDF (72/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
18. DSU (Debugging support unit )(MB86832/834)
(1)Instruction Address Descriptor Register (INSTADR) ASI = 0x01, Address = 0x0000ff00H to 0x0000ff04H
bit→ 31
Instruction Address Compare Data
21 0
Reserved
bit 31 to bit 2 :Instruction Address Compare Data (RST = 0x00000000H)
bit 1 to bit 0 :Reserved [“0”Write, Don’t care for read]
(2)Data Address Descriptor Register (DATAADR)
ASI = 0x01, Address = 0x0000ff08H to 0x0000ff0cH
bit→ 31
0
Data Address Compare Data
bit 31 to bit 0 :Data Address Compare Data (RST = 0x00000000H)
(3)Data Value Descriptor Register (DVDR)
bit→ 31
bit 31 to bit 0 :Data Value (RST = 0x00000000H)
Data Value
ASI = 0x01, Address = 0x0000ff10H
0
(4)Data Value Descriptor Register/Mask Register (DVDMSK)
bit→ 31
Data/Mask Value
bit 31 to bit 0 :Data/Mask Value (RST = 0x00000000H)
ASI = 0x01, Address = 0x0000ff14H
0
(5)Debug Control Register (DSUCR)
ASI = 0x01, Address = 0x0000ff18H
bit→
31
24 23
ASI Value2
16 15 14 13
987654321 0
ASI Value1
Reserved
bit 31 to bit 24 :ASI Value2 (RST = 0x00)
bit 23 to bit 16 :ASI Value1 (RST = 0x00)
bit 15
:Instruction User/Supervrisor2 (Supervrisor = 1, User = 0, RST = 0)
bit 14
:Instruction User/Supervrisor1 (Supervrisor = 1, User = 0, RST = 0)
bit 13 to bit 9 :Reserved
bit 8
:Enable Data Address2 Break (Enable = 1, Disable = 0, RST = 0)
bit 7
:Enable Data Address1 Break (Enable = 1, Disable = 0, RST = 0)
bit 6
:Enable Instruction Address2 Break (Enable = 1, Disable = 0, RST = 0)
bit 5
:Enable Instruction Address1 Break (Enable = 1, Disable = 0, RST = 0)
bit 4
:Single Step (On = 1, Off = 0, RST = 0)
bit 3 to bit 2 :Data Value Transaction Type (RST = 0x0)
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