MB86831 Datasheet, PDF (70/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
16. Interrupt controller (IRC)
(1)Trigger Mode 0 Register (TRGM0)
CS3# = L, Address<9:2> = 0x00
bit→ 31
Reserved
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 0 :Trigger Mode (High Level = 00, Low Level = 01, High Edge = 10, Low Edge = 11, RST = 00)
(2)Trigger Mode 1 Register (TRGM1)
CS3# = L, Address<9:2> = 0x01
bit→ 31
Reserved
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 0 0
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 2 :Trigger Mode (High Level = 00, Low Level = 01, High Edge = 10, Low Edge = 11, RST = 00)
bit 1 to bit 0 :Reserved [“0”Write, Read“0”]
(3)Request Sense Register (REQSNS)[Read only]
CS3# = L, Address<9:2> = 0x02
bit→ 31
Reserved
16 15
10
Request Sense 15 to Request Sense 1
0
bit 31 to bit 16 :Reserved [Don’t care for read]
bit 15 to bit 1 :Request Sense 15 to Request Sense 1 (RST = 0)
bit 0
:Reserved [Read“0”]
(4)Request Clear Register (REQCLR)[Wite only]
CS3# = L, Address<9:2> = 0x03
bit→ 31
Reserved
16 15
Request Clear 15 to Request Clear 1
10
0
bit 31 to bit 16 :Reserved [“0”Write]
bit 15 to bit 1 :Request Clear 15 to Request Clear 1 (Clear = 1, Not Clear = 0)
bit 0
:Reserved [“0”Write]
(5)Interrupt Mask Register (IMASK)
bit→ 31
Reserved
16 15
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 1 :Mask 15 to Mask 1 (Mask = 1, Not Mask = 0, RST = 1)
bit 0
:IRL Mask (Mask = 1, Not Mask = 0, RST = 0)
CS3# = L, Address<9:2> = 0x04
Mask 15 to Mask 1
10
IM
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