MB86831 Datasheet, PDF (76/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
(2)Bus Control Register
• Enable burst transfer after setting Cache Enable. To set Cache Disable, disable burst transfer in advance.
(3)System Support Control Register
• Set Cache Enable before setting DRAM Burst Enable. To set Cache Disable, disable the DRAM Burst Enable
bit.
• Before setting DRAM Burst Enable, be sure to set Burst Enable using the Bus Control Register.
• The SAMEPAGE# pin may become “L” at the first CS4 access after setting Same Page Enable.
• The Same Page circuit holds previous data even after the bus master is changed.
• Set the Same Page Mask Register before setting Same Page Enable to “1”.
• Before changing the Same Page Enable (bit 5) setting, set Cache Disable.
• Set all of the Address Range Specifier Registers and Address Mask Registers before setting CS Enable to
“1”. (Set all of the Address Range Specifier Registers and Address Mask Registers even if any CS is not to
be used.)
• Before changing the CS Enable (bit 4) setting, set Cache Disable.
• When setting the Programmable Wait-state, be sure to set the Wait State Specifier Register.
(4)Wait State Specifier Register
• Do not set the Wait Enable bit and the Single Cycle Non Burst Mode bit to “1” at the same time.
• If the Single Cycle Non Burst Mode bit is set to “1” in the burst mode, the ready signal is generated in one
cycle regardless of the setting of the Single Cycle Burst Mode bit.
• When setting the CS3 Wait State Specifier Register, be sure to set the Override bit to“1”. (The Wait State bit
can also be set to “1”.)
When the half-word load instruction is executed with CS3 in 16-bit Bus Mode, the CPU accesses twice but
the ready signal from the peripheral resource is generated only once. Therefore the CPU hangs at the second
access. To generate the second ready signal, set the Wait Enable bit to “1” (the CPU discards the data received
at the second access).
(5)Bus Width/Cacheable Register
• In the DRAM Controller Enable state with CS4# = “L”, CS5 is handled as a Non-Cacheable signal.
• In the DRAM Controller Enable state, the CS5 bus width follows the CS4 bus width setting. When the CS4
Bus Width Control bit has been set to (10) 2, for example, the CS5 bus width is forced to be set to (10) 2.
• The CS3 Bus Width can be set only to the 16-bit or 32-bit bus width. When the 16-bit bus width is set, use
Half-Word Load (address “0”) or Half-Word Store (address “0”) to access the interrupt controller (IRC) and
DRAM controller registers.
(6)DRAM Refresh Timer Register
• Be sure to set the Test Mode bit to “0”. Otherwise, TOVF# may not become “L”.
• Since the timer performs counting based on the external clock, it is not affected by the multiplier circuit.
(7)Sleep Mode Register
• To set the sleep mode (low power consumption mode), disable the caches.
• The instruction to set the sleep mode (low power consumption mode) must be followed by at least three NOP
instructions.
(8)Trigger Mode Register
• Set the Interrupt Mask Register to (ffff)16 before changing the Trigger mode.
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