MB86831 Datasheet, PDF (63/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
(2)Lock Control Register (LCR)
bit→ 31
Reserved
ASI= 0x01, Address= 0x00000004H
210
bit 31 to bit 2
bit 1
bit 0
:Reserved [“0”Write, Don’t care for read]
:Data Cache Entry Auto Lock (Enable = 1, Disable = 0, RST = 0)
:Instruction Cache Entry Auto Lock (Enable = 1, Disable = 0, RST = 0)
(3)Lock Control Save Register (LCSR)
bit→ 31
Reserved
ASI = 0x01, Address = 0x00000008H
210
bit 31 to bit 2
bit 1
bit 0
:Reserved [“0”Write, Don’t care for read]
:Previous Data Cache Auto Lock (Off = 0, On = 1, RST = 0)
:Previous Instruction Cache Auto Lock (Off = 0, On = 1, RST = 0)
(4)Restore Lock Control Register (RLCR)
bit→ 31
Reserved
ASI = 0x01, Address = 0x00000010H
10
bit 31 to bit 1 :Reserved [“0”Write, Don’t care for read]
bit 0
:Restore Lock Control Register (Restore = 1, Ignore = 0, RST = 0)
(5)Bus Control Register (BCR)
bit→ 31
Reserved
ASI = 0x01, Address = 0x00000020H
210
bit 31 to bit 2
bit 1
bit 0
:Reserved [“0”Write, Don’t care for read]
:Data Burst Enable (Enable = 1, Disable = 0, RST = 0)
:Instruction Burst Enable (Enable = 1, Disable = 0, RST = 0)
(6)System Support Control Register (SSCR)
bit→ 31
Reserved
ASI = 0x01, Address = 0x00000080H
876543210
bit 31 to bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1 to bit 0
:Reserved [“0”Write, Don’t care for read]
:DRAM Burst Enable (Enable = 1, Disable = 0, RST = 0)
:DRAM Controller Enable (Enable = 1, Disable = 0, RST = 0)
:Same Page Enable (Enable = 1, Disable = 0, RST = 0)
:CS Enable (Enable = 1, Disable = 0, RST = 0) *
:Programmable Wait-state (Enable = 1, Disable = 0, RST = 1)
:Timer On/Off (Enable = 1, Disable = 0, RST = 0)
:Reserved “0”Write, Don’t care for read]
*:CS0 is always enable.
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