MB86831 Datasheet, PDF (45/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
(Continued)
Classifica-
tion
(VDD5 = 3.3 V ± 0.15 V, VDD3 = 2.5 V ± 0.1 V, VSS = 0.0 V, TA = 0 °C to + 70 °C)
Parameter
Symbol
Value
Unit
Min.
Max.
Delay time
Hold time
RAS0# to RAS3#

15
ns
2

ns
DRAM-
Coutput
Delay time
Hold time
Delay time
Hold time
CAS0# to CAS3#
DWE0# to DWE3#

15
ns
2

ns

15
ns
2

ns
Delay time
Hold time
DOE#

15
ns
2

ns
Setup time
Asynchronous
ns
Hold time
IRC input
“H” level period
IRQ15 to IRQ8
Asynchronous
ns
2 × P + 10

ns
“L” level period
2 × P + 10

ns
P:Period (Cycle time)
* : RDYOUT# at the external ready mode is provided for from READY# input.
Notes
• Each parameter is valid within the specified ranges of temperatures and supply voltages unless otherwise
noted.
• Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5
V, the input level is 0.4 to 2.4 V, and the input rise time and fall time are 2 ns or less.
• Do not leave more than one output pins short-circuited for 1 second or more.
• The external output load capacitance is 30 pF.
• The specifications of pins other than those pins designated as asynchronous inputs and than the RDYOUT#
pin in external ready mode are determined by the rising edge of the external clock (CLKIN).
• These specifications are subject to change for improvement.
• The reset period requires at least 4 CLKIN cycles. The PLL oscillation stabilization delay time requires at least
4000 clock (CLKIN) pulses. For 40 MHz (25 ns) clock input, for example, the reset signal must therefore be
negated 100 µs later.
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