MB86831 Datasheet, PDF (65/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
(11)Bus Width/Cacheable Register (BWCR)
ASI = 0x01, Address = 0x0000016CH
bit→ 31
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved CS5 CS4 CS3 CS2 CS1 CS0 CS5 CS4 CS3 CS2 CS1
bit 31 to bit 24
bit 23,bit 21,bit 19,bit 17,bit 15,bit 13
bit 22,bit 20,bit 18,bit 16,bit 14,bit 12
bit 11 to bit 10,bit 9 to bit 8,bit 7 to bit 6,bit 5 to bit 4,
bit 3 to bit 2
bit 1 to bit 0
:Reserved [“0”Write, Don’t care for read]
:Internal/External Cacheable (0 = External, 1 = Internal)
:Cacheable (0 = cacheable, 1 = noncacheable)
:Bus Width Control bit
:Reserved [“0”Write, Don’t care for read]
(12)DRAM Refresh Timer Register (REFTMR)
ASI = 0x01, Address = 0x00000174H
bit→ 31 30
16 15
0
Reserved
Timer Value
bit 31
:Test Mode [“0“Write, Don’t care for read]
bit 30 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 0 :Timer Value (RST = 0xffff)
(13)DRAM Refresh Timer Pre-load (DRLD)
bit→ 31 30
Reserved
16 15
bit 31
:3 Cycle Mode (On = 1, Off = 0, RST = 0)
bit 30 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 0 :Timer Pre-load Value (RST = 0xffff)
ASI = 0x01, Address = 0x00000178H
0
Timer Pre-load Value
(14)Ancillary Version Register (VER2)[Read only]
bit→ 31
Reserved
16 15
ASI = 0x01, Address = 0x00020000H
0
Version
bit 31 to bit 16 :Reserved [Don’t care for read]
bit 15 to bit 0 :Version
(MB86831:Value = 0, MB86832:Value = 1, MB86833:Value = 2, MB86834:Value = 3,
MB86835:Value = 4, MB86836:Value = 1)
(15)Sleep Mode Register (SLPMD)[Write only]
bit→ 31
Reserved
bit 31 to bit 1 :Reserved
bit 0
:Sleep Mode (On = 1, Off = 0, RST = 0)
ASI = 0x01, Address = 0x00020004H
10
65