MB86831 Datasheet, PDF (58/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
5. Instruction Set
The MB86830 series is upward code-compatible with other SPARC processors. The MB86830 series now sup-
ports additional instructions to improve performance, which were previously not directly supported. In addition to
a set of already supported SPARC instructions, the MB86830 series has been provided with the integer multiply
and integer divide step instructions as well as the scan instruction for detecting “1” or “0” at the MSB.
For the list of supported instructions, see the instruction set below.
• Instruction set
LOGICAL
ARITHMETIC/SHIFT
DATA MOVEMENT
CONDITION CODES UNCHANGED
AND
CONDITION CODES UNCHANGED
ADD
TO USER/SUPERVISOR SPACE SIGNED
LOAD BYTE
OR
XOR
SUBTRACT
MULTIPLY (SIGNED/UNSIGNED)
LOAD HALF-WORD
LOAD WORD
AND
NOT
SCAN
SETHI
LOAD DOUBLE WORD
STORE BYTE
OR NOT
XNOR
CONDITION CODES SET
AND
OR
SHIFT LEFT LOGICAL
SHIFT RIGHT LOGICAL
SHIFT RIGHT ARITHMETIC
CONDITION CODES SET
ADD
STORE HALF-WORD
STORE WORD
STORE DOUBLE WORD
TO USER SPACE UNSIGNED
LOAD BYTE
XOR
AND NOT
SUBTRACT
MULTIPLY (SIGNED/UNSIGNED)
LOAD HALF-WORD
TO ALTERNATE SPACE SIGNED
OR NOT
XNOR
MULTIPLY STEP
DIVIDE STEP
LOAD BYTE
LOAD HALF-WORD
CONTROL TRANSFER
CONDITIONAL BRANCH
CONDITIONAL TRAP
CALL
RETURN
SAVE
RESTORE
JUMP AND LINK
EXTENDED AND CONDITION CODES
UNCHANGED
ADD
SUBTRACT
EXTENDED AND CONDITION CODES SET
ADD
SUBTRACT
TAGGED AND CONDITION CODES SET
(WITH AND WITHOUT TRAP ON OVERFLOW)
ADD
SUBTRACT
LOAD WORD
LOAD DOUBLE WORD
STORE BYTE
STORE HALF-WORD
STORE WORD
STORE DOUBLE WORD
TO ALTERNATE SPACE UNSIGNED
LOAD BYTE
LOAD HALF-WORD
ATOMIC OPERATION IN USER SPACE
SWAP WORD
READ/WRITE CONTROL REGISTER
LOAD/STORE UNSIGNED BYTE
READ PSR
WRITE PSR
READ TBR
WRITE TBR
READ WIM
WRITE WIM
READ Y
WRITE Y
RDASR
WRASR
ATOMIC OPERATION IN
ALTERNATE SPACE
SWAP WORD
LOAD/STORE UNSIGEND BYTE
6. Interrupts
One of the key criteria to determine whether a processor is suitable for embedded applications is whether the pro-
cessor can completely service interrupts within the minimum interrupt processing time. The processors implement-
ed as the MB86830 series guarantee not only short average wait time but also short maximum wait time.
The interrupt response time is the sum of the time for the processor to complete the current task after recognizing
an interrupt and the time for the processor to start executing the interrupt service routine. The MB86830 series
offers a variety of functions to minimize the both factors.
To minimize the time to complete the current task, the MB86830 series is designed so that the task can be inter-
rupted easily or it can be completed in a minimum of cycles. For this purpose, the MB86830 series implements
the cache system that updates only one word at a time using a prefetch buffer when a cache miss occurs, inter-
ruptible integer division using a divide step instruction, high-speed multiplication using a multiplier, and a 4-word
write buffer for processing a pending bus transaction.
To minimize the time required for starting executing the interrupt service routine, the processor switches the reg-
ister window to a new one upon detection of an interrupt. This function allows the service routine to be executed
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