MB86831 Datasheet, PDF (19/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
5. DDSU (Debug Support Unit) Related Pins (MB86832/834)
Symbol
Pin name
I/O
Function
EMUBRK# Emulator Break
Emulator Break pin.
When a reset is canceled, the EMUBRK# signal level is input to set a
I
mode in combination with the EMUENG# signal level.
The MB86832 contains a pull-up resistor (about 50 kΩ). Leave this pin
open when the DSU (debug support unit) is not used. The MB86834
has no pull-up resistor.
EMUENB#
Emulator Enable
Emulator Enable pin.
When a reset is canceled, the EMUENB# signal level is input to set a
mode in combination with the EMUBRK# signal level. When a reset is
canceled, this pin becomes an output pin after four clock cycles if either
I/O (DSUBRK# = DSUENB# = “L”) or (DSUBRK# = “H”, DSUENB# = “L”)
is set.
The MB86832 contains a pull-up resistor (about 50 kΩ). Leave this pin
open when the DSU (debug support unit) is not used. The MB86834
has no pull-up resistor.
EMUD<3:0>
Emulator Data pin.
This pin outputs traced instruction addresses divided into eight compo-
Emulator Data Bus
I/O
nents in the monitor mode. It also inputs instruction codes and outputs
instruction or data addresses in the DSU mode.
Since this pin serves as an output with the DSU disabled, leave the pin
open if the DSU (debug support unit) is not to be used.
EMUSD<3:0>
Emulator Status/
Data Bus
Emulator Status/Data pin.
This pin outputs the CPU status in the monitor mode and. It also inputs
I/O
instruction codes and outputs instruction or data addresses in the DSU
mode.
Since this pin serves as an output with the DSU disabled, leave the pin
open if the DSU (debug support unit) is not to be used.
6. Signals for the JTAG Test Port (MB86836)
Symbol
Pin name
I/O
Function
TCK
Test Clock
I
JTAG test clock input pin.
This pin has an internal pull-down resistor.
TMS
Test Mode
I
JTAG test mode selection pin.
This pin has an internal pull-down resistor.
TDI
Test Data In
I
JTAG test data input pin.
This pin has an internal pull-down resistor.
TDO
Test Data Out O JTAG test data output pin.
TRST#
Test Reset
I
JTAG test reset pin.
This pin is reset to “L”. It has an internal pull-down resistor.
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