MB86831 Datasheet, PDF (59/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
without saving the current register in advance. The user can also lock the service routine in the cache, allowing
faster processing with the routine. At this time, the on-chip data cache can be used as a high-speed local stack to
minimize the delay in accessing the routine variable in the service routine.
The MB86830 series has a maximum of 15 interrupt levels to directly support 15 interrupt sources. The highest
interrupt level is nonmaskable.
7. Caches
The MB86830 series incorporates independent data and instruction caches, allowing a high-performance system
to be constructed without the need for high-speed external memory or relevant control logics. The caches are
mapped onto physical addresses.
The instruction cache consists of: 64 units/2 banks on the MB86831/835, 128 units/2 banks on the MB86832/836,
256 units/2 banks on a 32-byte line on the MB86834, and 64 units/1 bank on a 16-byte line on the MB86833. The
data cache consists of: 64 units/2 banks on the MB86831/835, 64 units/1 bank on a 16-byte line on the MB86833,
128 units/2 banks on the MB86832/836, and 256 units/2 banks on a 32-byte line on the MB86834. (See “The com-
position of the data cache” and “The composition of the instruction cash.”) Each line is divided into 4-byte sub-
blocks. When a cache miss occurs, the cache is updated in one word (4 bytes) or four words (16 bytes), selectively.
Updating the cache in one word eliminates the wait time for an interrupt generated for replacing a long cache line;
updating the cache in four words can result improvement in cache hit rate.
Updating the cache in four words uses the burst mode. The instruction prefetch buffer fetches the next instruction
in advance, assuming that it corresponds to the next instruction cache miss.
The caches can be used in the normal mode or in either of two lock modes. In the normal mode, the cache in two-
way set-associative configuration replaces one of two corresponding entries using the LRU (Least Recently Used)
algorithm. As an alternate method, the entire cache or only the selected entry can be locked depending on the lock
mode in use. The lock mode can lock a time-critical routine in the cache. The global cache lock mode locks the
entries in the entire instruction or data cache.
The two control bits in the cache control register enable or disable the lock in the instruction and data caches. Once
an entire cache is locked, any valid entry in the cache cannot be replaced. To ensure optimum performance, how-
ever, an invalid entry is updated when it is accessed. This update is performed automatically without generating
time penalty.The instruction or data entry selected by local cache locking can be locked automatically in the corre-
sponding cache. This mechanism can ensure the fastest response from a certain important interrupt routine by
locking the code of the routine in the cache.
Also, of those routines which can be removed from the cache, frequently used ones should be given priority in per-
formance in some cases. In such cases, the entries can be locked.
The local cache lock mode can lock individual entries or lock entries automatically by hardware. To lock each entry,
the lock bit in the corresponding cache tag line is set by software. For automatic cache locking, the lock function
is enabled or disabled depending on the bit in the corresponding cache control register. The enable/disable bit is
set at the beginning of the routine for which the entry is to be locked. The location of cache access generated with
the bit enabling the lock function is locked in the cache. Automatic cache locking does not involve overhead other
than the initial setting cycle.
When a cache entry is unlocked, the data cache assign the cache entry only at load time based on the write-
through update policy. The write operation is buffered and the processor can continue execution while data is be-
ing written back to memory. In contrast, the data written to the locked data cache location is not written to main
memory.
The above method reduces external bus access and allows part of the data cache to be used as on-chip RAM
which is not mapped into external memory.
The data and instruction caches are designed to be accessed through the independent data and instruction buses
to load/write data from/to the cache at a maximum speed of 1 CPI (Clock/Instruction).
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