MB86831 Datasheet, PDF (64/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
(7)Same Page Mask Register (SPGMR)
bit→ 31 30
23 22
ASI<7:0>Mask
ASI = 0x01, Address = 0x00000120H
10
Address<31:10>Mask
bit 31
:Reserved [“0”Write, Don’t care for read]
bit 30 to bit 23 :ASI<7:0>Mask (Care = 0, Don’t Care = 1, RST = X)
bit 22 to bit 1 :Address<31:10>Mask (Care = 0, Don’t Care = 1, RST = X)
bit 0
:Reserved [“0”Write,Don’t care for read]
X:Don’t care
(8)Address Range Specifier Register (ARSR)
bit→ 31 30
23 22
ASI<7:0>
ASI = 0x01, Address = 0x00000124H to 0x00000134H
10
Address<31:10>
bit 31
:Reserved [“0”Write, Don’t care for read]
bit 30 to bit 23 :ASI<7:0>(RST = X) *
bit 22 to bit 1 :Address<31:10>(RST = X) *
bit 0
:Reserved [“0”Write, Don’t care for read]
*CS0 is fixed to Address<31: 15>=0,Address<14: 10>=0,ASI<7:0>=0x09.
X:Don’t care
(9)Address Mask Register (AMR)
bit→ 31 30
23 22
ASI<7:0>Mask
ASI = 0x01, Address = 0x00000140H to 0x00000154H
10
Address<31:10>Mask
bit 31
:Reserved [“0”Write, Don’t care for read]
bit 30 to bit 23 :ASI<7:0>Mask (CS0:RST = 0, CS1 to CS5:RST = X)
bit 22 to bit 1 :Address<31:10>Mask (CS0:RST = <31:15> = 0, <14:10> = 0x1f, CS1 to CS5:RST = X)
bit 0
:Reserved [“0”Write, Don’t care for read]
X:Don’t care
(10)Wait State Specifier Register (WSSR)
ASI = 0x01, Address = 0x00000160H to 0x00000168H
bit→ 31
27 26
22 21 20 19 18
14 13
9 876543
0
count 1 count 2
count 1
count 2
bit 31 to bit 27,bit 18 to bit 14
bit 26 to bit 22,bit 13 to bit 9
bit 21,bit 8
bit 20,bit 7
bit 19,bit 6
bit 5,bit 4
bit 3 to bit 0
:count 1 (CS0:RST = 0x1f, CS1 to CS5:RST = 0)
:count 2 (CS0:RST = 0x1f, CS1 to CS5:RST = 0)
:Wait Enable (On = 1, Off = 0,CS0:RST = 1, CS1 to CS5:RST = 0)
:Single Cycle Non Burst Mode (On = 1, Off = 0,RST = 0)
:Override (On = 1, Off = 0, CS0 = 1, CS1 to CS5 = 0)
:Single Cycle Burst Mode (On = 1, Off = 0, RST = 0)
:Reserved [“0”Write, Don’t care for read]
64