MB86831 Datasheet, PDF (12/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
(Continued)
Symbol
BE0#
BE1#
BE2#
BE3#
CS0#
CS1#
CS2#
CS3#
CS4#
CS5#
Pin name
BYTE ENABLE
CHIP SELECT
I/O
Function
(Continued)
Width of
bus
Access type
BE0# BE1# BE2# BE3#
Byte-0 (D<15:8>)
1000
Byte-1 (D<7:0>)
0100
Byte-2 (D<15:8>)
1010
Byte-3 (D<7:0>)
0110
Width of ^Write _{Half word-0 (D<15:0>) 0 0 0 0}
16-bits
bus
Half word-1 (D<15:0>) 0 0 1 0
Word (D<15:0>) access-0 0 0 1 0
Word (D<15:0> )access-1 0 0 0 0
Read
Access-0
Access-1
0000
0010
Byte-0
XX0 0
O
Byte-1
XX0 1
O
Byte-2
XX1 0
I/O
O
Byte-3
XX1 1
Half word-0 access-1 X X 0 1
Write
Width of
8-bits
bus
Half word-0 access-0
Half word-1 access-0
Half word-1 access-1
word access-0
word access-1
XX0 0
XX1 1
XX1 0
XX1 1
XX1 0
word access-2
XX0 1
word access-3
XX0 0
Access-0
XX0 0
Read
Access-1
Access-2
XX0 1
XX1 0
Access-3
XX1 1
* : The mark such as (D<31:24>) shows the bit of the data bus used.
Chip select signals.
These chip select signals are asserted when the Address Range Spec-
O
ifier Register (ARSR) and Address Mask Register (AMR) is accessed
with the CS Enable bit (bit 4) in the System Support Control Register
(SSCR) set to “1.” (Note, however, that only the CS0# pin is indepen-
dent of the CS Enable bit.)
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