MB86831 Datasheet, PDF (67/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
(3)Instruction Cache Tag (ICTAG)
bit→ 31
Address Tag
ASI = 0x0c
Capacity 16 KB
Bank 1:Address = 0x00000000H to 0x00001fe0H (+32)
Bank 2:Address = 0x80000000H to 0x80001fe0H (+32)
Capacity 8 KB
Bank 1:Address = 0x00000000H to 0x00000fe0H (+32)
Bank 2:Address = 0x80000000H to 0x80000fe0H (+32)
Capacity 4 KB
Bank 1:Address = 0x00000000H to 0x000007e0H (+32)
Bank 2:Address = 0x80000000H to 0x800007e0H (+32)
Capacity 2 KB
Bank 1:Address = 0x00000000H to 0x000003f0H (+16)
Bank 2:Address = 0x80000000H to 0x800003f0H (+16)
Capacity 1 KB
Bank 2:Address = 0x80000000H to 0x800003f0H (+16)
13 12 11 10 9
654
210
bit 31 to bit 13 :Address Tag (RST = X)
bit 12
:Capacity 16 KB = <Reserved>, Other = <Address Tag>
bit 11
:Capacity 16 KB, 8 KB = <Reserved>, Other = <Address Tag>
bit 10
:Capacity 16 KB, 8 KB, 4 KB = <Sub Block Valid>(Valid = 1, Invalid = 0, RST = 0)
Capacity 2 KB, 1 KB = <Address Tag>
bit 9 to bit 6 :Sub Block Valid (Valid = 1, Invalid = 0,RST = 0)
bit 4 to bit 2 :Capacity 16 KB, 8 KB, 4 KB = <Sub Block Valid>(Valid = 1, Invalid = 0, RST = 0)
Capacity2 KB, 1 KB = <Reserved> [Don’t care for read]
bit 5
:User/Supervisor (User = 0, Supervisor = 1, RST = X)
bit 1
:Capacity1 KB = <Reserved>, Other= LRU (RST = 0) *
bit 0
:Entry Lock (Lock = 1, Unlock = 0, RST = 0)
*:BANK only, BANK 2 is Reserved
X:Don’t care
(4)Instruction Cache Invalidate Register (ICINVLD)[Wite only]
ASI = 0x0c
Capacity 16 KB
Bank 1:Address = 0x00008000H
Bank 2:Address = 0x80008000H
Other
Bank 1:Address = 0x00001000H
Bank 2:Address = 0x80001000H
bit→ 31
Reserved
bit 31 to bit 2 :Reserved [“0”Write]
bit 1
:Cache LRU, Lock Bit Clear (Clear = 1, Not Clear = 0)
bit 0
:Valid Bit Clear (Clear = 1, Not Clear = 0)
210
67