MB86831 Datasheet, PDF (54/82 Pages) Fujitsu Component Limited. – 32-bit Embedded Controller

MB86830 Series
s ARCHITECTURE
The MB86830 series is a line of 32-bit RISC processors running at an operating frequency of 100 MHz, providing
high performance of 121 VAX-MIPS. As products belong to the Fujitsu SPARClite family, the MB86830 series is
based on the SPARC architecture and are thus upward code-compatible with the conventional products in the
SPARClite family. The MB86830 series was developed in particular for embedded applications, providing high per-
formance and high level of integration when used as embedded controllers.
The MB86830 series has an efficient set of instructions and is hardwired so that most of them can be executed in
one cycle. The IU (integer unit) features five pipelined execution stages designed for processing data interlocks,
providing a branch handler optimized for for efficient transition of control and a bus interface for processing one-
cycle bus access for on-chip memory.
The internal register file consisting of a stack of eight windows, made up of 136 registers in total, speeds up inter-
rupt response and context switching. The register file minimizes memory access during procedure linkage and
facilitates parameter passing and variable assignment.
The MB86830 series contains instruction and data caches to isolate processor operation from external memory.
These caches are designed for highest flexibility so that it can lock each entry to improve the performance of the
entire system.
The independent instruction and internal data buses serve as high-bandwidth interfaces between the IU (integer
unit) and the on-chip caches. These buses support single-cycle instruction execution and single-cycle data trans-
fer between the IU and caches in parallel.
The MB86830 series incorporates an integer multiplier and auxiliary hardware for division. The MB86830 series
can therefore execute 32-bit integer multiplication in five cycles, 16-bit integer multiplication in three cycles, 8-bit
integer multiplication in two cycles, and integer multiplication by 0 in one cycle.
1. Main Features
(1)High-speed execution of instructions
Most of the instructions in most programs are simple, designing the programs so as to execute such simple instruc-
tions as fast as possible dramatically improves the program execution time.
(2)High-capacity register set
The register set reduces the number of required accesses to data memory. Registers are organized into a stack
of groups called register windows, allowing themselves to be used efficiently for high-priority tasks such as interrupt
services and operating system working registers. A stack of (overlapping) register windows also contributes to sim-
plifying parameter passing during procedure linkage, thereby reducing the code size of most programs.
(3)On-chip caches
The MB86830 series incorporates data and instruction caches so that the processor can work independently of the
slower memory subsystem. These caches are implemented in two-way set-associative configuration on the
MB86831/832; they are directly mapped on the MB86833.
(4)Locking entries in caches
The MB86830 series can lock both of data and instruction entries in their respective caches, ensuring high perfor-
mance in processing important or frequently called routines. Each cache offers maximum flexibility so that entries
can be locked in all or selective part of the cache.
(5)Bus interface
The MB86830 series supports programmable chip selection, a wait state generator, and fast page mode DRAM,
minimizing the necessity of connecting external circuits.
(6)On-chip DRAM controller
The on-chip DRAM controller supports fast page mode and EDO DRAMs. It also controls self-refreshing of DRAM
in sleep mode (low power consumption mode).
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