MB86294 Datasheet, PDF (64/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
6.5 D i s p l a y S c a n C o n t r o l
6.5.1 Applicable display
The following table shows typical display resolutions and their synchronous signal frequencies. The pixel
clock frequency is determined by setting the division rate of the display reference clock. The display
reference clock is either the internal PLL (400.9 MHz at input frequency of 14.318 MHz), or the clock
supplied to the DCLKI input pin. The following table gives the clock division rate used when the internal
PLL is the display reference clock:
Table 4-1 Resolution and Display Frequency
Resolution
320 × 240
400 × 240
480 × 240
640 × 480
854 × 480
800 × 600
1024 × 768
Division rate
of reference
clock
1/60
1/48
1/40
1/16
1/12
1/10
1/6
Pixel
frequency
6.7 MHz
8.4 MHz
10.0 MHz
25.1 MHz
33.4 MHz
40.1 MHz
66.8 MHz
Horizontal
total pixel
count
424
530
636
800
1062
1056
1389
Horizontal
frequency
Vertical
total raster
count
15.76 kHz
263
15.76 kHz
263
15.76 kHz
263
31.5 kHz
525
31.3 kHz
525
38.0 kHz
633
48.1 kHz
806
Vertical
frequency
59.9 Hz
59.9 Hz
59.9 Hz
59.7 Hz
59.9 Hz
60.0 Hz
59.9 Hz
Pixel frequency = 14.318 MHz × 28 × reference clock division rate (when internal PLL selected)
= DCLKI input frequency × reference clock division rate (when DCLKI selected)
Horizontal frequency = Pixel frequency/Horizontal total pixel count
Vertical frequency = Horizontal frequency/Vertical total raster count
MB86294/294S CORAL_LB
Graphics Controller
64
Specifications Rev. 1.0