MB86294 Datasheet, PDF (260/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
12.1.5 CPU read/write timing diagram in V832 mode (Normally Not Ready
Mode)
( MODE[2:0]=010, RDY_MODE=0, BS_MODE=0)
T1 Tsw1 Thw1 T2 T1 Tsw1 Thw1 Thw2 Thw3 T2
BCLKI
A[23:2]
XCS
XB1CYST
XMRD(XIORD)
D[31:0] ^Hi-Z
XMWR(XIOWR)
XXXBEN[3:0]
Valid Data
OUT
Valid Data
Hi-Z
OUT
D[31:0]
Valid Data IN
Valid Data IN
XREADY
Hi-Z
Hi-Z
SoftWaiit HardWait Ready
SoftWait HardWait HardWait HardWait Ready
T1: Read/write start cycle (XREADY in not ready state)
¡: XREADY sampling in V832 mode
×: Soft Wait (1 cycle) in V832 mode
Tsw*: Software wait insertion cycle
Twh*: Hardware wait insertion cycle (XREADY asserts Ready after the preparations)
T2: Read/write end cycle (XREADY ends in not ready state)
Notes: 1.The XxxBEN signal is used only for a write from the CPU; it is not used for a read from the
CPU.
2.The CPU always inserts one cycle wait after read access.
Fig. 10.5 Read/Write Timing Diagram in V832 Mode (Normally Not Ready Mode)
MB86294/294S CORAL_LB
Graphics Controller
260
Specifications Rev. 1.0