MB86294 Datasheet, PDF (151/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
11.2.1 Host interface registers
DTC (DMA Transfer Count)
Register
address
HostBaseAddress + 00H
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
DTC
R/W
R0
RW
Initial value
0
Don’t care
DTC is a readable/writable 32-bit register which sets the transfer count in either one long-word (32 bits) or
32 bytes units. When “1h” is set transfer is performed once. However, when “0h” is set, it indicates the
maximum transfer count and 16M (16,777,216) data are transferred. During DMA transfer, the remaining
transfer count is shown, therefore, the register value cannot be overwritten until DMA transfer is
completed.
Note: This register need not be set in a mode in which Dual DMA ACK is not used, or the V832 mode.
DSU (DMA Set Up)
Register
address
HostBaseAddress + 04H
Bit number
7
Bit field name
6
5
4
Reserved
R/W
R0
Initial value
0
3
2
1
0
DAM
DBM
DW
RW
RW
RW
0
0
0
Bit 0 DW (DMA Word)
Specifies DMA transfer count
0: 1-double word (32 bits) per DMA transfer
1: 8-double words (32 bytes) per DMA transfer (only SH4)
Bit 1 DBM (DMA Bus request Mode)
Selects DREQ mode used in DMA transfer in dual-address mode
0: DREQ is not negated during DMA transfer irrespective of cycle steal or burst mode.
1: DREQ is negated irrespective of cycle steal or burst mode when CORAL cannot receive
data (that is, when Ready cannot be returned immediately). When CORAL is ready to
receive data, DREQ is reasserted (When DMA transfer is performed in the single-address
mode, DREQ is controlled automatically).
Bit 2 DAM (DMA Address Mode)
Selects DMA address mode in issuing external request
0: Dual address mode
1: Single address mode (SH4 only)
Bit 3 DNA (Dual address No Ack mode)
This bit is selected when using the dual-address-mode DMA that does not use the ACK signal.
0: Uses dual-address-mode DMA that uses ordinary ACK signal
1: Uses dual-address-mode DMA that does not use ACK signal
Detection of the DREQ edge is supported; DREQ is negated per transfer. When data
cannot be received irrespective of the Bit1 setting, DREQ continues being negated.
MB86294/294S CORAL_LB
Graphics Controller
151
Specifications Rev. 1.0