MB86294 Datasheet, PDF (280/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
12.3.3 Composite synchronous signal
When the EEQ bit of the DCM register is “0”, the CSYNC signal output waveform is as shown below.
CSYNC
VSYNC
even field
odd field
CSYNC
VSYNC
odd field
even field
Fig 10.28 Composite Synchronous Signal without Equalizing Pulse
When the EEQ bit of the DCM register is “1”, the equalizing pulse is inserted into the CSYNC signal,
producing the waveform shown below.
CSYNC
VSYNC
CSYNC
VSYNC
even field
odd field
odd field
even field
Fig 10.29 Composite Synchronous Signal with Equalizing Pulse
The equalizing pulse is inserted when the vertical blanking time period starts. It is also inserted three
times after the vertical synchronization time period has elapsed.
CAUTIONS
12.4 C P U C a u t i o n s
MB86294/294S CORAL_LB
Graphics Controller
280
Specifications Rev. 1.0