MB86294 Datasheet, PDF (34/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
• Coral can be connected to the Hitachi SH4 (SH7750), SH3 (SH7709) NEC V832 and Fujitsu SPARClite
(MB86833) without external circuit. In the SRAM interface mode, Coral can be used with any other CPU
as well. The host CPU is specified by the MODE0 to 2 pins.
MODE 2
L
L
L
L
H
MODE 1
L
L
H
H
X
MODE 0
L
H
L
H
X
SH3
SH4
V832
SPARClite
Reserved
CPU
When the bus cycle terminates, a ready signal level can be set. When using the RDY_MODE signal at
“High” level, set two cycles as the CPU software wait of the CPU. (When BS_MODE = “High” level, set
the CPU software wait to three cycles.)
RDY_ MODE
L
H
Ready signal mode
When the bus cycle terminates, sets the XRDY signal to the ‘not ready’ level.
When the bus cycle terminates, sets the XRDY signal to the ‘ready’ level.
A CPU with no BS (Bus Start) pin can be used. Setting can be performed in all CPU modes.
Connection can be made to a CPU with no BS signal by setting the BS_MODE signal to “High” level.
When not using the BS signal, fix the BS pin of CORAL at “High” level.
When using the BS_MODE signal as “High” level in the normally ready mode, set the CPU software wait
to three cycles.
BS_ MODE
L
H
BS signal mode
Connect to a CPU with the BS signal
Connect to a CPU without the BS signal
The data signal is 32 bits (fixed).
The address signal is 32 bits (per one double-word) × 24, and has a 64-Mbyte address field. (16-MByte
address space is provided for V832 and SPARClite.)
The external bus operating frequency is up to 100 MHz.
In the SH4, V832, and SPARClite modes, when the XRDY signal is low, it is in the ready state. However,
in the SH3 mode, when the XRDY signal is low, it is in the wait state. This signal is a tri-state output that
is synchronized with the rising edge of BCLKI.
DMA data transfer is supported using an external DMA controller.
An interrupt signal is generated to the host CPU.
The XRST input must be kept low for at least 300 µs after setting the S (PLL reset) signal to high.
In the V832 mode, Coral signals are connected to the V832 CPU as follows:
A24
DTACK
DRACK
CORAL Pins
XMWR
XTC
DMAAK
V832 Signals
MB86294/294S CORAL_LB
Graphics Controller
34
Specifications Rev. 1.0