MB86294 Datasheet, PDF (278/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
12.3 Display Timing
12.3.1 Non-interlace mode
Ri/Gi/Bi
DISPE
HSYNC
VSYNC
VTR+1 rasters
VSP+1 rasters
VDP+1 rasters
VSW+1 rasters
Assert Frame interrupt
Assert VSYNC interrupt
Ri/Gi/Bi
DISPE
HSYNC
DCLKO
Ri/Gi/Bi
DISPE
Latency=14clocks
HDP+1 clocks
HSP+1 clocks
HTP+1 clocks
HSW+1 clocks
123
n-2 n-1
n = HDP+1
Fig. 10.26 Non-interlace Timing
In the above diagram, VTR, HDP, etc., are the setting values of their associated registers.
The VSYNC/frame interrupt is asserted when display of the last raster ends. When updating display
parameters, synchronize with the frame interrupt so no display disturbance occurs. Calculation for the
next frame is started immediately after the vertical synchronization pulse is asserted, so the
parameters must be updated by the time that calculation is started.
MB86294/294S CORAL_LB
Graphics Controller
278
Specifications Rev. 1.0