MB86294 Datasheet, PDF (271/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
12.1.18 Dual-address DMA (without ACK) end timing
/DREQ
Right to use bus
CPU
DMAC CPU DMAC
CPU
Fig. 10.18 Dual-address DMA (without ACK) End Timing
Example: DMA operation when DMA transfer performed twice
(1) The CPU accesses the DREQ issue register (DRQ) of Coral to issue DREQ.
(2) The right to use bus is transferred from the CPU to the DMAC.
(3) In the first DMAC cycle, write is performed to CORAL and DREQ is negated; DREQ is reasserted in
the next cycle.
(4) The right to use bus is returned to the CPU and the DREQ edge is detected, so the right to use bus is
transferred to the DMAC.
(5) The second write operation is performed and DREQ is negated, but DREQ is reasserted because
CORAL does not recognize that the transfer has ended.
(6) The right to use bus is transferred to the CPU, so the CPU writes to the DTS register of CORAL to
negate DREQ.
MB86294/294S CORAL_LB
Graphics Controller
271
Specifications Rev. 1.0