MB86294 Datasheet, PDF (262/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
12.1.7 CPU read/write timing diagram in SPARClite (Normally Not Ready
Mode)
( MODE[2:0]=011, RDY_MODE=0, BS_MODE=0)
T1 Tsw1 Thw1 T2
T1 Tsw1 Thw1 Thw2 Thw3 T2
CLKINI
ADR[23:2]
CS#
AS#
RDWR#
Hi-Z
D[31:0]
Valid Data
Hi-Z
Valid Data
RDWR#
BE[3:0]#
D[31:0]
Valid Data IN
Valid Data IN
READY#
Hi-Z
Hi-Z
Hi-Z
SoftWaiit HardWait Ready
SoftWait HardWait HardWait HardWait Ready
T1: Read/write start cycle (READY# in not ready state)
¡: READY# sampling in SPARClite
×: Soft Wait (1 cycle) in SPARClite
Tsw*: Software wait insertion cycle
Twh*: Hardware wait insertion cycle (READY# asserts Ready after the preparations)
T2: Read/write end cycle (READY# ends in not ready state)
Note: BE# signal is used only for a write from the CPU; it is not used for a read from the CPU.
Fig. 10.7 Read/Write Timing Diagram in SPARClite (Normally Not Ready Mode)
MB86294/294S CORAL_LB
Graphics Controller
262
Specifications Rev. 1.0