MB86294 Datasheet, PDF (162/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
When n is set, with Offset = 0, the frequency division rate is 1/(2n + 2).
When m is set, with Offset = 100h, the frequency division rate is 1/(m + 1).
Basically, these are setting parameters with the same function (2n + 2 = m + 1).
Because of this, m = 2 n + 1 is established. When n is set to the SC field with Offset = 0,
2n + 1 is reflected with Offset = 100h.
Also, when PLL is selected as the reference clock, frequency division rates 1/1 to 1/5 are
non-functional even when set; other frequency division rates are assigned.
Bit 15
CKS (Clock Source)
Selects reference clock
0: Internal PLL output clock
1: DCLKI input
MB86294/294S CORAL_LB
Graphics Controller
162
Specifications Rev. 1.0