MB86294 Datasheet, PDF (275/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
12.2.4 Timing of write access to different row addresses
MCLKO
MRAS
TRAS
MCAS
TRCD
MWE
MA
ROW
COL
TRP
TRCD
ROW
COL
MD
DATA
DQM
ROW: Row Address
COL: Column Address
DATA: READ DATA
TRAS: RAS Active Time
TRCD: RAS to CAS Delay Time
TRP: RAS Precharge Time
DATA
Fig. 10.22 Timing of Write Access to Different Row Addresses
The above timing diagram shows that write access is made from CORAL to different row addresses of
SDRAM. The first and next address to be write fall across an SDRAM page boundary, so the
Pre-charge command is issued at the timing satisfying TRAS, and then after the elapse of TRP, the
ACTV command is reissued, and then the WRITE command is issued.
MB86294/294S CORAL_LB
Graphics Controller
275
Specifications Rev. 1.0