MB86294 Datasheet, PDF (33/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
2.3 P i n F u n c t i o n
2.3.1 Host CPU interface
Pin name
MODE0-2
RDY_MODE
BS_MODE
XRST
D0-31
A2-A25
BCLKI
XBS
XCS
XRD
XWE0
XWE1
XWE2
XWE3
XRDY
DREQ
DRACK/DMAAK
DTACK/XTC
XINT
Table 2-1 Host CPU Interface Pins
I/O
Input
Input
Input
Input
In/Out
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Tri-state
Output
Input
Input
Output
Description
Host CPU mode select
Normally ready, Not ready select
BS signal with/without select
Hardware reset
Host CPU bus data
Host CPU bus address (In the V832 mode, A[24] is
connected to XMWR.)
Host CPU bus clock
Bus cycle start signal
Chip select signal
Read strobe signal
Write strobe for D0 to D7 signal
Write strobe for D8 to D15 signal
Write strobe for D16 to D23 signal
Write strobe for D24 to D31 signal
Wait request signal (In the SH3 mode, when this signal is
“0”, it indicates the wait state; in the SH4, V832 and
SPARClite modes, when this signal is “1”, it indicates the
wait state.)
DMA request signal (This signal is low-active in both the SH
mode and V832 mode.)
Acknowledge signal in response to DMA request (DMAAK is
used in the V832 mode; this signal is high-active in both the
SH mode and V832 mode.)
DMA transfer strobe signal (XTC is used in the V832 mode.
In the SH mode, this signal is high-active; in the V832 mode,
it is low-active.)
Interrupt signal issued to host CPU (In the SH mode, and
SPARClite this signal is low-active; in the V832 mode, it is
high-active)
MB86294/294S CORAL_LB
Graphics Controller
33
Specifications Rev. 1.0