MB86294 Datasheet, PDF (35/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
2.3.2 Video output interface
Pin name
DCLKO
DCLKI
HSYNC
VSYNC
CSYNC
DISPE
GV
R7-0
G7-0
B7-0
XRGBEN
AOUTR
AOUTG
AOUTB
ACOMPR
ACOMPG
ACOMPB
VREF
VRO
Table 2-2 Video Output Interface Pins
I/O
Output
Input
I/O
I/O
Output
Output
Output
Output
Output
Output
Input
Analog Output
Analog Output
Analog Output
Analog
Analog
Analog
Analog
Analog
Description
Dot clock signal for display
Dot clock signal input
Horizontal sync signal output
Horizontal sync input <in external sync mode>
Vertical sync signal output
Vertical sync input <in external sync mode>
Composite sync signal output
Display enable period signal
Graphics/video switch
Digital picture (R) output. These signals are multiplexed
MD53-MD46. These pins are available when XRGEN = 0.
Digital picture (G) output. These signals are multiplexed
MD45-MD38. These pins are available when XRGEN = 0.
Digital picture (B) output. These signals are multiplexed
MD37-MD32 and MDQM7-6. These pins are available when
XRGEN = 0.
Signal to switch between RGB1-0 output, capture singnals
/memory bus (MD 63-MD32,MDQM7,6)
Analog Signal (R) output
Analog Signal (G) output
Analog Signal (B) output
Analog (R) Compensation output
Analog (G) Compensation output
Analog (B) Compensation output
Analog Volatage Reference input
Analog Reference Current output
It is possible to output digital RGB, when XRGBEN = 0.(Memory bus=32bit)
Additional setting of external circuits can generate composite video signal.
Synchronous to external video signal display can be performed.
Either mode which is synchronous to DCLKI signal or one which is synchronous to dot clock, as for
normal display can be selected.
Since HSYNC and VSYNC signals are set to input state after reset, these signals must be pulled up LSI
externally.
The GV signal switches graphics and video at chroma key operation. When video is selected, the “Low”
level is output.
AOUTR, AOUTG and AOUTB must be terminated at 75 ohm.
1.1-V is input to VREF. A bypass capacitor( with good high-frequency characteristics) must be inserted
between VREF and AVS.
ACOMPR, ACOMPG and ACOMPB are tied to analog VDD via 0.1uF ceremic capacitors.
VRO must be pulled down to analog ground by a 2.7 k ohm resister.
MB86294/294S CORAL_LB
Graphics Controller
35
Specifications Rev. 1.0