MB86294 Datasheet, PDF (268/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
12.1.14 SH4 single-address DMA transfer end timing
BCLKIN
D[31:0]
DREQ
DRACK
Acceptance
Acceptance
DTACK
Last data
¡: DREQ sampling and channel priority determination for SH mode (DREQ = level detection)
Fig. 10.14 SH4 Single-address DMA Transfer End Timing
DREQ is negated three cycles after DRACK is written as the last data.
12.1.15 SH3/4 dual-address DMA transfer end timing
BCLKIN
DREQ
DRACK
A[24:2]
D[31:0]
Source address
Read
Destination address
Write
DTACK
For the CORAL, the read/write operation is performed according to the SRAM protocol.
Fig. 10.15 SH3/4 Dual-address DMA Transfer End Timing
DREQ is negated three cycles after DRACK is written as the last data.
Note: When the dual address mode (DMA) is used, the DTACK signal is not used.
MB86294/294S CORAL_LB
Graphics Controller
268
Specifications Rev. 1.0