MB86294 Datasheet, PDF (192/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
DLS (Display Layer Select)
Register
address
DisplayBaseAddress + 180H
Bit number 31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
DLS5
DLS4
DLS3
DLS2
DLS1
DSL0
R/W
R0
R0 RW R0 RW R0 RW R0 RW R0 RW R0 RW
Initial value
101
100
011
010
001
000
This register defines the blending sequence.
Bit 3 to 0
DSL0 (Display Layer Select 0)
Selects the top layer subjected to blending.
0000 L0 layer
0001 L1 layer
:
:
0101 L5 layer
0110 Reserved
:
:
0110 Reserved
0111 Not selected
Bit 7 to 4
DSL1 (Display Layer Select 1)
Selects the second layer subjected to blending. The bit values are the same as DSL0.
Bit 11 to 8
DSL2 (Display Layer Select 2)
Selects the third layer subjected to blending. The bit values are the same as DSL0.
Bit 15 to 12 DSL3 (Display Layer Select 3)
Selects the fourth layer subjected to blending. The bit values are the same as DSL0.
Bit 19 to 16 DSL4 (Display Layer Select 4)
Selects the fifth layer subjected to blending. The bit values are the same as DSL0.
Bit 23 to 20 DSL5 (Display Layer Select 5)
Selects the bottom layer subjected to blending. The bit values are the same as DSL0.
MB86294/294S CORAL_LB
Graphics Controller
192
Specifications Rev. 1.0