MB86294 Datasheet, PDF (168/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
L0OA (L0 layer Origin Address)
Register
address
DisplayBaseAddress + 24H
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name Reserved
L0OA
R/W
R0
RW
R0
Initial value
0
Don’t care
0000
This register sets the origin address of the logic frame of the L0 layer. Since lower 4 bits are fixed at
“0”, address 16-byte-aligned.
L0DA (L0-layer Display Address)
Register
address
DisplayBaseAddress + 28H
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name Reserved
L0DA
R/W
R0
RW
Initial value
0
Don’t care
This register sets the display origin address of the L0 layer. For the direct color mode (16 bits/pixel),
the lower 1 bit is “0”, and this address is treated as being aligned in 2 bytes.
L0DX (L0-layer Display position X)
Register
address
DisplayBaseAddress + 2CH
Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
L0DX
R/W
R0
RW
Initial value
0
Don’t care
This register sets the display starting position (X coordinates) of the L0 layer on the basis of the origin
of the logic frame in pixels.
L0DY (L0-layer Display position Y)
Register
address
DisplayBaseAddress + 2EH
Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
L0DY
R/W
R0
RW
Initial value
0
Don’t care
This register sets the display starting position (Y coordinates) of the L0 layer on the basis of the origin
of the logic frame in pixels.
MB86294/294S CORAL_LB
Graphics Controller
168
Specifications Rev. 1.0