MB86294 Datasheet, PDF (266/305 Pages) Fujitsu Component Limited. – Grraphiics Controller specifications

FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
12.1.11 SH3/4 dual-address DMA (transfer of 1 long word)
BCLKIN
DREQ
A[24:2]
D[31:0]
Source address
Read
Destination address
Write
Source address
Read
Destination address
Write
For the CORAL, the read/write operation is performed according to the SRAM protocol.
Fig. 10.11 SH3/4 Dual-address DMA (Transfer of 1 Long Word)
In the dual-address mode, the DREQ signal is kept asserted until the transfer ends by default.
Consequently, when CORAL cannot return the ready signal immediately, in order to negate the DREQ
signal set the DBM register.
12.1.12 SH3/4 dual-address DMA (transfer of 8 long words)
BCLKIN
DREQ
A[24:2]
D[31:0]
Source address
………
Read 1
Read 2 ……… Read 8
………
Destination address
………
Write 1
Write 2 ……… Write 8
………
For the CORAL, the read/write operation is performed according to the SRAM protocol.
Fig. 10.12 SH3/4 Dual-address DMA (Transfer of 8 Long Words)
In the dual-address mode, the DREQ signal is kept asserted until the transfer ends by default.
Consequently, when CORAL cannot return the ready signal immediately, in order to negate the DREQ
signal set the DBM register.
MB86294/294S CORAL_LB
Graphics Controller
266
Specifications Rev. 1.0