MC9S12UF32 Datasheet, PDF (98/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
A.1.3 Pins
There are six groups of functional pins.
A.1.3.1 3.3V/5.0V I/O pins on VDDX
Those I/O pins have a nominal level of 3.3V or 5.0V depending on the voltage supplied by VDDX. This
group of pins is comprised of all port I/O pins.The internal structure of all those pins is identical, however
some of the functionality may be disabled.
A.1.3.2 3.3V/5.0V I/O pins on VDD3X
Those I/O pins have a nominal level of 3.3V or 5.0V depending on the voltage supplied by VDD3X. This
group of pins is comprised of all port I/O pins.The internal structure of all those pins is identical, however
some of the functionality may be disabled.
A.1.3.3 5.0V I/O pins
Those I/O pins have a nominal level of 5.0V with power rail connecting to VDDR. This group of pins is
comprised of all port I/O pins.The internal structure of all those pins is identical, however some of the
functionality may be disabled.
A.1.3.4 USB physical layer interface analog pins
Those I/O pins have specific analog function dedicated to the USB PHY interface and are supplied by
internally generated 3.3V VDDA.
A.1.3.5 Oscillator
The pins EXTAL and XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by
internal 2.5V regulator.
A.1.3.6 TEST
This pin is used for production testing only and must be tied to VSS in normal application.
A.1.4 Current Injection
Power supply must maintain regulation within operating specified range during instantaneous and
operating maximum current conditions. If positive injection current (V_in > supply rail voltage) is greater
than supply current of the pin group, the injection current may flow out of supply rail and could result in
external power supply going out of regulation. Insure external supply load will shunt current greater than
maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if
no system clock is present, or if clock rate is very low which would reduce overall power consumption.
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