MC9S12UF32 Datasheet, PDF (70/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
used as a timing reference. The ECLK frequency is equal to 1/2 the crystal frequency out of reset. The
ECLK output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in
the MODE register and the ESTR bit in the EBICTL register. All clocks, including the ECLK, are halted
when the MCU is in STOP mode. It is possible to configure the MCU to interface to slow external
memory. ECLK can be stretched for such accesses. The PE4 pin is initially configured as ECLK output
with stretch in all expanded modes. Reference the MISC register (EXSTR[1:0] bits) for more information.
In normal expanded narrow mode, the ECLK is available for use in external select decode logic or as a
constant speed clock for use in the external application system.
2.5.20 PE3 / LSTRB / TAGLO / CFA3 — Port E I/O Pin 3 / Low-Byte Strobe
(LSTRB)
PE3 can be used as a general-purpose I/O in all modes and is an input with an active pull-up out of reset.
PE3 can also be configured as a Low-Byte Strobe (LSTRB). The LSTRB signal is used in write operations,
so external low byte writes will not be possible until this function is enabled. LSTRB can be enabled by
setting the LSTRE bit in the PEAR register. In Expanded Wide and Emulation Narrow modes, and when
BDM tagging is enabled, the LSTRB function is multiplexed with the TAGLO function. When enabled a
logic zero on the TAGLO pin at the falling edge of ECLK will tag the low byte of an instruction word
being read into the instruction queue. In single chip mode, this port can be configured as address pin for
CFHC. Refer to Table 2-2 for module routing information. For further functional information, do refer
to CFHC block guide.
2.5.21 PE2 / R/W — Port E I/O Pin 2 / Read/Write
PE2 can be used as a general-purpose I/O in all modes and is configured an input with an active pull-up
out of reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR
register. External writes will not be possible until the read/write function is enabled.
2.5.22 PE0 / XIRQ — Port E input Pin 0 / Non Maskable Interrupt Pin
PE0 is always an input and can always be read. The PE0 pin is also the XIRQ input for requesting a
non-maskable asynchronous interrupt to the MCU. During reset, the X bit in the condition code register
(CCR) is set and any XIRQ interrupt is masked until MCU software enables it by clearing the X bit.
Because the XIRQ input is level sensitive triggered, it can be connected to a multiple-source wired-OR
network. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can
be turned off by clearing PUPEE in the PUCR register.
2.5.23 PJ2 / ATACS1 / SWP / CFCE2 / ROMCTL - Port J I/O Pin 2
PJ2 is a general purpose input or output pin. In expanded modes the PJ2 pin can be used to determine the
reset state of the ROMON bit in the MISC register. At the rising edge of RESET, the state of the PJ2 pin
is latched to the ROMON bit. This pin can be used as CFCE2 of CFHC module, ATACS1 of ATA5HC
module or SWP of SMHC module. Refer to Table 2-2 for module routing information. While in reset and
immediately out of reset the PJ2 pin is configured as a high impedance input pin. Consult the Port
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