MC9S12UF32 Datasheet, PDF (92/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
14.1 Device-specific information
The PIM is part of the IPBus domain.
The MODRR register within the PIM allows for pin mapping for the 100LQFP package and for the 64
LQFP package.
Section 15 Serial Communication Interface (SCI) Block
Description
Consult the SCI Block Guide for information about the Serial Communication Interface module.
15.1 Device-specific information
The SCI is part of the IPBus domain.
The register spaces for the timer is located at addresses $00C8-$00CF.
Section 16 Secured Digital Host Controller (SDHC) Block
Description
Consult the SDHC Block Guide for information about the Secured Digital host controller module.
16.1 Device-specific information
The SDHC is part of the IQUE bus domain.
The register spaces for the SDHC is located at addresses $02C0-$02DF.
Section 17 Smartmedia Host Controller (SMHC) Block
Description
Consult the SMHC Block Guide for information about the Smartmedia host controller module.
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