MC9S12UF32 Datasheet, PDF (62/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
2.4.32 PP6 / SWE / ACFD14 / AATAD14— Port P I/O Pin 6
PP6 are general purpose input or output pin. When enabled in the SMHC module, the PP6 pin becomes
the write enable pin, SWE. When the SMHC is not enabled, it can be configured in the PIM module to
become the alternate data pins for CFHC or ATA5HC in place of PA6. While in reset and immediately out
of reset PP6 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM)
PIM_9UF32 Block Guide, the CFHC Block Guide, the ATA5HC Block Guide and the MSHC Block
Guide for information about pin configurations.
2.4.33 PP5 / SALE / ACFD13 / AATAD13— Port P I/O Pin 5
PP5 are general purpose input or output pin. When enabled in the SMHC module, the PP5 pin becomes
the address latch enable pin, SALE. When the SMHC is not enabled, it can be configured in the PIM
module to become the alternate data pins for CFHC or ATA5HC in place of PA5. While in reset and
immediately out of reset PP5 pin is configured as a high impedance input pin. Consult the Port Integration
Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide, the ATA5HC Block Guide and the
MSHC Block Guide for information about pin configurations.
2.4.34 PP4 / SCLE / ACFD12 / AATAD12— Port P I/O Pin 4
PP4 are general purpose input or output pin. When enabled in the SMHC module, the PP4 pin becomes
the command latch enable pin, SCLE. When the SMHC is not enabled, it can be configured in the PIM
module to become the alternate data pins for CFHC or ATA5HC in place of PA4. While in reset and
immediately out of reset PP4 pin is configured as a high impedance input pin. Consult the Port Integration
Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide, the ATA5HC Block Guide and the
MSHC Block Guide for information about pin configurations.
2.4.35 PP3 / SWP / ACFD11 / AATAD11— Port P I/O Pin 3
PP3 are general purpose input or output pin. When enabled in the SMHC module, the PP3 pin becomes
the write protect pin, SWP. When the SMHC is not enabled, it can be configured in the PIM module to
become the alternate data pins for CFHC or ATA5HC in place of PA3. While in reset and immediately out
of reset PP3 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM)
PIM_9UF32 Block Guide, the CFHC Block Guide, the ATA5HC Block Guide and the MSHC Block
Guide for information about pin configurations.
2.4.36 PP2 / SCE / ACFD10 / AATAD10— Port P I/O Pin 2
PP2 are general purpose input or output pin. When enabled in the SMHC module, the PP2 pin becomes
the chip enable pin, SCE. When the SMHC is not enabled, it can be configured in the PIM module to
become the alternate data pins for CFHC or ATA5HC in place of PA2. While in reset and immediately out
of reset PP2 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM)
PIM_9UF32 Block Guide, the CFHC Block Guide, the ATA5HC Block Guide and the MSHC Block
Guide for information about pin configurations.
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