MC9S12UF32 Datasheet, PDF (2/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

Revision History
Release
Number
Date
00.01 17JAN02
00.02 19FEB02
00.03 26APR02
00.04 16SEP02
00.05 25SEP02
00.06 03JUN03
00.07 11JUN03
00.08 13JUL03
Author
Y.H. Cheng
Y.H. Cheng
Y.H. Cheng
Y.H. Cheng
Y.H. Cheng
Y.H. Cheng
Y.H. Cheng
Y.H. Cheng
Summary of Changes
Initial Version
Modified SMRAM mapping to allow 1k byte 16-bit block mappable
to Vector Space. Update spec with review feedback.
Modified Device pinout to separate D+ D- for high speed and low
speed operation. Remap Timer pins to Port R. Update BG
references.
Modified Device pinout per IP requirement
Add SCI
Update Interrupt information.
Change pin location for REF3V and VREGEN
minor update on module name references
remove references to pseudo stop and clock monitor
- Updated info for SMRAM3P5K2E in device memory map
- Updated EXTAL and XTAL supply rail information.
- Relocate SCI module base address from $70 to $C8
- Relocate ATA5HC module base address from $240 to $1C0
- Relocate PIM module base address from $80 to $240
- Relocate Interrupt Vectors
- Updated Phy evaluation pinout.
- Updated CFA00, CFA01 and CFA02 pin name to CFA0, CFA1 and
CFA2 respectively.
- Removed ESD and Latchup section in Electrical.
- Update Block Guide References
- Miscellaneous Typo mistakes.
- Update typo in interrupt vector table for Vector $C2
- Update typo in pin order of IOC[7:4] in signal properties table
- Specify run and wait IDDs in Electrical Section
- Specify stop IDD at room temperature in Electrical Section
- Change specification to include 64 pin option
- ROMCTL pin assigned to PJ2
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