MC9S12UF32 Datasheet, PDF (73/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
2.5.34 PS7 / CFRDY(CFIREQ) / ATAINTQ / MSSDIO — Port S I/O Pin 7
PS7 is a general purpose input or output pin. This pin can be configured as MSSDIO signal of the MSHC
module; ATAINTQ signal of the ATA5HC module or the CFRDY/CFIREQ signal of the CFHC module.
Refer to Table 2-2 for module routing information. While in reset and immediately out of reset the PS7
pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9UF32
Block Guide, the MSHC Block Guide, the CFHC Block Guide and the ATA5HC Block Guide for
information about pin configurations.
2.5.35 PS6 / CFWE / ATADMARQ / MSCLK — Port S I/O Pin 6
PS6 is a general purpose input or output pin. This pin can be configured as MSCLK signal of the MSHC
module; ATADMARQ signal of the ATA5HC module or the CFWE signal of the CFHC module. Refer
to Table 2-2 for module routing information. While in reset and immediately out of reset the PS6 pin is
configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9UF32 Block
Guide, the CFHC Block Guide, the MSHC Block Guide and the ATA5HC Block Guide for information
about pin configurations.
2.5.36 PS5 / TXD — Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can also be configured as the TXD pin when the SCI
module. While in reset and immediately out of reset the PS5 pin is configured as a high impedance input
pin. Consult the Serial Communication Interface (SCI) Block Guide for more information.
2.5.37 PS4 / RXD — Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can also be configured as the RXD pin when the SCI
module. While in reset and immediately out of reset the PS4 pin is configured as a high impedance input
pin. Consult the Serial Communication Interface (SCI) Block Guide for more information.
2.5.38 PT1 / IOC1 / SDDATA3 / SWE / CFOE — Port T I/O Pin 1
PT1 is a general purpose input or output pin. This pin can be configured as IOC1 of TIM_16B8 module,
SDDATA3 signal of the SDHC module; SWE signal of the SMHC module or the CFOE signal of the
CFHC module. Refer to Table 2-2 for module routing information. While in reset and immediately out
of reset the PT1 pin is configured as a high impedance input. Consult the SDHC Block Guide, SMHC
Block Guide, CFHC Block Guide, Port Integration Module (PIM) PIM_9UF32 Block Guide and the
TIM_16B8C Block Guide for information about pin configurations.
2.5.39 PT0 / IOC0 / SDDATA0 / SRE / CFREG — Port T I/O Pin 0
PT0 is a general purpose input or output pin. This pin can be used as CFREG of CFHC module, IOC0 of
TIM_16B8 module, SDDATA0 of SDHC module or SRE of SMHC module. Refer to Table 2-2 for
module routing information. While in reset and immediately out of reset the PT0 pin is configured as a
high impedance input. Consult the SDHC Block Guide, SMHC Block Guide, CFHC Block Guide, Port
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