MC9S12UF32 Datasheet, PDF (115/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

A.4 Reset, Oscillator and PHY
System on a Chip Guide — 9S12UF32DGV1/D V01.05
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
USB Physical Layer (PHY).
A.4.1 Startup
Table A-12 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG_U) Block User Guide.
Table A-12 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol Min
1
T POR release level
V_PORR
2
T POR assert level
V_PORA
0.97
3
D Reset input pulse width, minimum input time
PW_RSTL
2
4
D Startup from Reset
n_RST
192
5
D
Interrupt pulse width, IRQ edge-sensitive
mode
PW_IRQ
20
6
D Wait recovery startup time
t_WRS
Typ
Max
2.07
196
14
Unit
V
V
t_osc
n_osc
ns
t_cyc
A.4.1.1 POR
The release level V_PORR and the assert level V_PORA are derived from the V_DD Supply. They are also valid
if the device is powered externally. After releasing the POR reset, the oscillator is started.
A.4.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when V_DD is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG_U Flags Register has not been set.
A.4.1.3 External Reset
When external reset is asserted for a time greater than PW_RSTL, the CRG_U module generates an internal
reset, and the CPU starts fetching the reset vector if there was an oscillation before reset.
A.4.1.4 Stop Recovery
Out of STOP, the controller can be woken up by an external interrupt.
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