MC9S12UF32 Datasheet, PDF (100/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
A device will be defined as a failure if after exposure to ESD pulses, the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model
Human Body
Machine
Latch-up
Description
Series Resistance
Storage Capacitance
Number of Pulse per pin
positive
negative
Series Resistance
Storage Capacitance
Number of Pulse per pin
positive
negative
Minimum input voltage limit
Maximum input voltage limit
Symbol
R1
C
-
R1
C
-
Value
1500
100
-
1
1
0
200
-
1
1
-2.5
7.5
Unit
Ohm
pF
Ohm
pF
V
V
Table A-3 ESD and Latch-Up Protection Characteristics
Num C
Rating
1 C Human Body Model (HBM)
2 C Machine Model (MM)
Latch-up Current at T_A = 70°C
3 C positive
negative
Symbol
V_HBM
V_MM
I_LAT
Min
2000
200
+100
-100
Max
-
-
-
Unit
V
V
mA
A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.
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