MC9S12UF32 Datasheet, PDF (93/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
17.1 Device-specific information
The SMHC is part of the IQUE bus domain.
The register spaces for the SMHC is located at addresses $02B0-$02BF.
Section 18 Smartmedia RAM (SMRAM) Block Description
Consult the SMRAM Block Guide for information about the Smartmedia RAM module.
18.1 Device-specific information
The SMRAM is part of the HCS12 Bus domain.
The register space for the SMRAM is located at addresses $011C-$011F.
The memory space for the SMRAM is located at addresses $0800-$1FFF upon reset and is mappable to
any 8k-byte boundary.
Section 19 Timer (TIM) Block Description
Consult the TIM_16B8C Block Guide for information about the Timer module.
19.1 Device-specific information
The TIM is part of the IPBus domain.
The register spaces for the timer is located at addresses $0040-$006F.
Section 20 USB2.0 Controller (USB20D6E2F) Block
Description
Consult the USB20D6E2F Block Guide for information about the USB2.0 Device Controller module.
20.1 Device-specific information
The USB 2.0 Serial Interface Engine (USB20SIE) is part of the IQUE bus domain.
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