MC9S12UF32 Datasheet, PDF (23/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
1.4 Block Diagram
32K Byte Flash EEPROM
VDDR
VSSR
VREGEN
VDD
VDDA
REF3V
BKGD
EXTAL
XTAL
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
TEST
3.5K Byte SMRAM
Voltage Regulator
Single-wire Background
Debug Module
Clock and
Reset
Generation
Module
XIRQ
IRQ
R/W
LSTRB
ECLK
MODA
MODB
NOACC
CPU12
Periodic Interrupt
COP Watchdog
Breakpoints
System
Integration
Module
(SIM)
I/O Driver 3.3/5V
VDDX
VSSX
I/O Driver 3.3/5V
VDD3X
VSS3X
Voltage Regulator 5V & I/O
VDDR
VSSR
Internal Logic 2.5v
VDD
Timer
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
SCI
RX
TX
Multiplexed Address/Data Bus
Port Multiplexer
DDRA
PTA
DDRB
16
PTB
Multiplexed
Wide Bus
Multiplexed
Narrow Bus
RPU
RREF
DPF
DMF
DPH
DMH
USB2.0
Physical
Interface
(PHY)
USB2.0
Serial
Interface
Engine
(SIE)
1.5K byte
Endpoint
Buffer
Integrated
Queue
Module
(IQUE)
16
Q-bus (60MHz)
16
SWE
SALE
SCLE
SWP
SMHC _SCE
SCD
16
SRE
SBSY
SDAT[0-7]
BS
16
MSHC SDIO
SCLK
CMD
CLK
16
SDHC
DAT0
DAT1
DAT2
DAT3
16
ATA5HC
16
CFHC
* This block diagram shows only one particular module to port routing. Detail module routing for different
applications can be found in Signal Description Section.
* Some pins are not available in 100-pin package.
* IPbus runs at 1/2 frequency of S12 core bus, which is controlled by REFDV register of CRG_U module.
*Qbus refers to the data transfer channels between IQUE and USB/ATA5HC/CFHC/MSHC/SDHC/SMHC.
PHY Analog 3.3V
VDDA
VSSA
PT0
PT1
PT2
PT3
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PQ0
PQ1
PQ2
PQ3
PQ4
PQ5
PQ6
PQ7
PJ0
PJ1
PJ2
PM0
PM1
PM2
PM3
PM4
PM5
PU0
PU1
PU2
PU3
PU4
PU5
PR0
PR1
PR2
PR3
PR4
PR5
PR6
PR7
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PWROFF5V
PWROFF3V
Figure 1-1 MC9S12UF32 Block Diagram
Freescale Semiconductor
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