MC9S12UF32 Datasheet, PDF (94/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
The USB 2.0 Physical Layer (USB20PHY) is an analog plus high speed digital hard block.
The register spaces for the USB20D6E2F is located at addresses $0300-$03FF.
Section 21 Voltage Regulator (VREG_U) Block Description
Consult the VREG_U Block Guide for information about the voltage regulator.
21.1 Device-specific information
The VREG_U is part of the IPBus domain.
In 64-pin LQFP package version, the regulator enable pin (VREGEN) is not available externally and is
connected internally to VDDR.
Section 22 Schematic and PCB Layout Design
Recommendations
This section provides recommendations for schematic and PCB layout design for implementing an USB
interface with the MC9S12UF32 microcontroller unit (MCU).
22.1 Schematic Design with the MC9S12UF32 and a USB interface
Figure 22-1 is a schematic of a MC9S12UF32 64-pin package minimum system implementation
configured in single-chip mode and utilizing the internal voltage regulator. Same connections can be used
with MC9S12UF32 100-pin package. The schematic provides a reference for the following
MC9S12UF32 design items:
• Operation mode
• Clocks
• Power
• USB connector (CON1)
• Background debug connector (CON2)
To configure the MC9S12UF32 in normal single-chip mode, the MODC, MODB, and MODA pins should
be configured as documented in the device overview chapter of this book.
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