MC9S12UF32 Datasheet, PDF (104/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol Min
P _{Input High Voltage}¹
1
T _{Input High Voltage}¹
V_IH
0.65*V_DD5
V_IH
-
P _{Input Low Voltage}¹
2
T _{Input Low Voltage}¹
V_IL
-
V_IL
V_SS5 - 0.3
3 C Input Hysteresis
V_HYS
Input Leakage Current (pins in high ohmic input
4
P _{mode)2 Vin = VDD5 or VSS5}
I_in
–2.5
Output High Voltage (pins in output mode)¹
5 P ^{Partial Drive IOH = –2.5mA}
Full Drive IOH = –12.5mA
V_OH
V_DD5 – 0.8
Output Low Voltage (pins in output mode)
6 P ^{Partial Drive IOL = +2.5mA}
Full Drive IOL = +12.5mA
V_OL
-
Internal Pull Up Device Current, except PM0,
7 P ^{PM[4-2], PU[1-0], PS2 and PS[7-6], tested at V}_IL
I_PUL
-
Max.
Internal Pull Up Device Current, except PM0,
8 P ^{PM[4-2], PU[1-0], PS2 and PS[7-6], tested at V}_IH
I_PUH
-10
Min.
Internal Pull Down Device Current, except PQ[0-7],
9 P ^{PP1, PP[5-3], PM0, PM[5-2], PJ[2-0], PU[1-0], PS2}
I_PDH
-
and PS[7-6], tested at V_IH Min.
Internal Pull Down Device Current, except PQ[0-7],
10 P ^{PP1, PP[5-3], PM0, PM[5-2], PJ[2-0], PU[1-0], PS2}
I_PDL
10
and PS[7-6], tested at V_IL Max.
11
P
Internal Pull Up Device Resistance for PM0, PM[4-2],
PJ[2-0], PU[1-0], PS2 and PS[7-6].
I_PUA
12
12
P
Internal Pull Down Device Resistance for PM0,
PM[4-2], PU[1-0], PS2 and PS[7-6].
I_PDA
14
13
P
Internal Pull Down Device Resistance for PQ[0-7],
PP1, PP[5-3], PJ[2-0]
I_PDB
80
14 P Internal Pull Down Device Resistance for PM5
I_PDC
56
15 D Input Capacitance
C_in
Injection current³
16 T _{Single Pin limit}
Total Device Limit. Sum of all injected currents
I_ICS
-2.5
I_ICP
-25
Typ
-
-
-
-
250
-
-
-
-
-
-
-
15
18
100
70
6
-
Max Unit
-
V
V_DD5 + 0.3 V
0.35*V_DD5 V
-
V
mV
2.5
µA
-
V
0.8
V
–130
µA
-
µA
130
µA
-
µA
18
kΩ
22
kΩ
120
kΩ
84
kΩ
-
pF
2.5
mA
25
104
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