MC9S12UF32 Datasheet, PDF (35/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
$01C0 - $01FF
ATA Host Controller (ATA5HC)
Address
Name
$01E5 HUDMA9 (lo) ^Read:
Write:
$01E6 -
$01ED
Reserved
Read:
Write:
$01EE
DCTR/DASR^{1 Read:}
(hi)
Write:
$01EF ^{DCTR/DASR1 Read:}
(lo)
Write:
$01F0
DDR (hi)¹
Read:
Write:
$01F1
DDR (lo)¹
Read:
Write:
$01F2
DFR/DER (hi)¹
Read:
Write:
$01F3
DFR/DER (lo)¹
Read:
Write:
$01F4
DSCR (hi)¹
Read:
Write:
$01F5
DSCR (lo)¹
Read:
Write:
$01F6
DSNR (hi)¹
Read:
Write:
$01F7
DSNR (lo)¹
Read:
Write:
$01F8
DCLR (hi)¹
Read:
Write:
$01F9
DCLR (lo)¹
Read:
Write:
$01FA
DCHR (hi)¹
Read:
Write:
$01FB
DCHR (lo)¹
Read:
Write:
$01FC
DDHR (hi)¹
Read:
Write:
$01FD
DDHR (lo)¹
Read:
Write:
$01FE
DCR/DSR (hi)¹
Read:
Write:
$01FF
HDMAM (lo)
Read:
Write:
Bit 7
0
0
BSY
0
0
0
0
0
0
obs
0
BSY
PIE
Bit 6
0
0
DRDY
0
0
0
0
0
0
#1
0
DRDY
HUT
Bit 5
0
Bit 4
0
0
0
#
0
0
Bit 3
0
0
DRQ
0
Bit 2
0
Bit 1
0
0
0
obs
SRST nIEN
0
0
Bit 0
0
0
ERR
ZERO
0
BYTE_E
BYTE_O
#r1
ABRT
#r2
#w
0
0
0
0
0
0
#
0
0
0
0
0
0
#
0
0
0
0
0
0
#
0
0
0
0
0
0
#
0
0
0
0
0
0
obs
DEV
0
0
0
#r
DRQ
#w
AF
0
IE
#2
0
0
obs
UDMA
RD
0
ERR
WR
NOTES:
1. These registers are mapped to the registers on an external ATA/ATAPI device, for detail explanation of the #, #r1,
#r2, #w, #1,#2 field, please refer to the ATAHC block guide and ATA/ATAPI standards.
Freescale Semiconductor
35