MC9S12UF32 Datasheet, PDF (106/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
Table A-7 3.3V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol Min
P _{Input High Voltage}¹
1
T _{Input High Voltage}¹
V_IH
0.65*V_DD3
V_IH
-
P _{Input Low Voltage}¹
2
T _{Input Low Voltage}¹
V_IL
-
V_IL
V_SS3 - 0.3
3 C Input Hysteresis
V_HYS
Input Leakage Current (pins in high ohmic input
4 P _{mode)2 Vin = VDD3 or VSS3}
I_in
–2.5
Output High Voltage (pins in output mode)¹
5 P ^{Partial Drive IOH = –0.75 mA}
Full Drive IOH = – 4.5 mA
V_OH
V_DD3 – 0.4
Output Low Voltage (pins in output mode)
6 P ^{Partial Drive IOL = +0.9 mA}
Full Drive IOL = +5.5 mA
V_OL
-
Internal Pull Up Device Current,PM0, PM[4-2],
7 P _{PJ[2-0], PU[1-0], PS2 and PS[7-6], tested at VIL Max.} I_PUL
-
Internal Pull Up Device Current,PM0, PM[4-2],
8 P _{PJ[2-0], PU[1-0], PS2 and PS[7-6], tested at VIH Min.} I_PUH
-6
Internal Pull Down Device Current,PQ[0-7], PP1,
9 P ^{PP[5-3], PM0, PM[5-2], PJ[2-0], PU[1-0], PS2 and}
I_PDH
-
PS[7-6]. tested at V_IH Min.
Internal Pull Down Device Current,PQ[0-7], PP1,
10 P ^{PP[5-3], PM0, PM[5-2], PJ[2-0], PU[1-0], PS2 and}
I_PDL
6
PS[7-6], tested at V_IL Max.
11
P
Internal Pull Up Device Resistance for PM0, PM[4-2],
PJ[2-0], PU[1-0], PS2 and PS[7-6].
I_PUA
12
12
P
Internal Pull Down Device Resistance for PM0,
PM[4-2], PU[1-0], PS2 and PS[7-6].
I_PDA
14
13
P
Internal Pull Down Device Resistance for PQ[0-7],
PP1, PP[5-3], PJ[2-0]
I_PDB
80
14 P Internal Pull Down Device Resistance for PM5
15 D Input Capacitance
I_PDC
56
C_in
Injection current³
16 T _{Single Pin limit}
Total Device Limit. Sum of all injected currents
I_ICS
-2.5
I_ICP
-25
NOTES:
1. V_DD3 refers to 3.3v supply voltage (VDDX, VDD3X).
Typ
-
-
-
-
250
-
-
-
-
-
-
-
15
18
100
70
6
-
Max Unit
-
V
V_DD3 + 0.3 V
0.35*V_DD3 V
-
V
mV
2.5
µA
-
V
0.4
V
–60
µA
-
µA
60
µA
-
µA
18
kΩ
22
kΩ
120
kΩ
84
kΩ
-
pF
2.5
mA
25
106
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