MC9S12UF32 Datasheet, PDF (53/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
Pin Name Pin Name
Function Function
1
2
Pin Name
Function
3
Internal Pull
Pin Name
Function
4
Supply
Rail
Resistor
CTRL
Reset
State
Description
PR[2]
CFA[5]
RXD
—
VDDX
PERR
PPSR
Disabled
Port R I/O Pin; CFHC address line,
SCI RXD
PR[3]
CFA[6]
TXD
—
VDDX
PERR
PPSR
Disabled
Port R I/O Pin; CFHC address line,
SCI TXD
PR[7:4] CFA[10:7] IOC[7:4]
—
VDDX
PERR
PPSR
Disabled
Port R I/O Pins; CFHC address
lines, Timer Channel 4 to 7
PS7
CFRDY/
IREQ
ATAINTQ
—
VDDX
PERS/
PPSS
Disabled
Port S I/O Pin; CFHC RDYIREQ
signal; ATA INTQ signal
PS6
CFWE ATADMARQ
—
VDDX
PERS/
PPSS
Disabled
Port S I/O Pin; CFHC WE signal;
ATA DMARQ signal
PS5
CFIOWR ATAIOWR
—
VDDX
PERS/
PPSS
Disabled
Port S I/O Pin; CFHC IOWR signal;
ATA IOWR signal
PS4
CFIORD ATAIORD
—
VDDX
PERS/
PPSS
Disabled
Port S I/O Pin; CFHC IORD signal;
ATA IORD signal
PS3
CFCE2
ATACS1
—
VDDX
PERS/
PPSS
Disabled
Port S I/O Pin; CFHC CE2 signal;
ATA CS2 signal
PS2
CFIOIS16
—
PS1
CFOE
—
—
VDDX
PERS/
PPSS
Disabled
Port S I/O Pin; CFHC IOIS16
signal
—
VDDX
PERS/
PPSS
Disabled
Port S I/O Pin; CFHC OE signal
PS0
CFCE1
ATACS0
—
VDDX
PERS/
PPSS
Disabled
Port S I/O Pin; CFHC CE1 signal;
ATA CS0 signal
PT[0:2] IOC[0:2] _CFA[0:2]²
—
VDD3X
PERT/
PPST
Disabled
Port T I/O Pins; Timer channels 0
to 2; CFHC address line
PT[3]
IOC[3]
CFWE²
—
VDD3X
PERT/
PPST
Disabled
Port T I/O Pins; Timer channels 3;
CFHCWE signal
PU5
CFA2
ATADA2
—
VDDX
PERU/
PPSU
Disabled
Port U I/O Pins; CFHC Address
signal; ATA Address signal
PU4
CFA1
ATADA1
—
VDDX
PERU/
PPSU
Disabled
Port U I/O Pins; CFHC Address
signal; ATA Address signal
PU3
CFA0
ATADA0
—
VDDX
PERU/
PPSU
Disabled
Port U I/O Pins; CFHC Address
signal; ATA Address signal
PU2
CFREG
—
—
VDDX
PERU/
PPSU
Disabled
Port U I/O Pins; CFHC REG signal
PU1 CFINPACK ATADMACK
—
PU0
CFWAIT ATAIORDY
—
VDDX
VDDX
PERU/
PPSU
Disabled
Port U I/O Pins; CFHC INPACK
signal; ATA DMACK signal
PERU/
PPSU
Disabled
Port U I/O Pins; CFHC WAIT
signal; ATA IORDY signal
NOTES:
1. This pin must be tied to VSS in Application
2. CFHC module port routing when bit 4 of MODRR is set to 1.
3. PJ2 is used as the ROMCTL signal during reset.
Freescale Semiconductor
53