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MC9S12UF32 Datasheet, PDF (68/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05
System on a Chip Guide — 9S12UF32DGV1/D V01.05
2.5.8 DPH - USB High Speed D+ data line
DPH is the D+ analog input output line for high speed data communication in the USB physical layer
module. This line will be high impedance during full speed operation. Refer to USB20D6E2F block guide
for further information.
2.5.9 DMF - USB Full Speed D- data line
DMF is the D- analog input output line for full speed data communication in the USB physical layer
module. This line is also used for D+ termination during high speed operation. Refer to USB20D6E2F
block guide for further information.
2.5.10 DMH - USB High Speed D- data line
DMH is the D- analog input output line for high speed data communication in the USB physical layer
module. This line will be high impedance during full speed operation. Refer to USB20D6E2F block guide
for further information.
2.5.11 REF3V - 3.3V reference for external regulator
REF3V a regulator reference for driving an external NMOS device to provide the system with a regulated
3.3V supply. The feedback path for the REF3V is the VDD3X supply pin. Refer to VREG_U block guide
for further information.
2.5.12 PA[5:0] / ADDR[13:8] / DATA[13:8] / CFD[13:8] / ATAD[13:8] — Port A
I/O Pins
PA[5:0] are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus. In single chip mode, this port can be configured as
SDHC function, data bus for CFHC or ATA5HC. Refer to Table 2-2 for module routing information. For
further functional information, do refer to SDHC, CFHC and ATA5HC block guide.
2.5.13 PA[6] / ADDR[14] / DATA[14] / CFD[14] / ATAD[14] / MSBS— Port A I/O
Pins
PA[6] is a general purpose input or output pin. In MCU expanded modes of operation, this pin is used for
the multiplexed external address and data bus. In single chip mode, this port pin can be configured as
MSBS signal for MSHC function, data bus pin for CFHC or ATA5HC. Refer to Table 2-2 for module
routing information. For further functional information, do refer to MSHC, CFHC and ATA5HC block
guide.
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