MC9S12UF32 Datasheet, PDF (119/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

A.5 External Bus Timing
System on a Chip Guide — 9S12UF32DGV1/D V01.05
A timing diagram of the external multiplexed-bus is illustrated in Figure A-1 with the actual timing
values shown on table Table A-15. All major bus signals are included in the diagram. While both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.5.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
ECLK
PE4
Addr/Data
(read)
PA, PB
5
9
data
Addr/Data
(write)
data
PA, PB
1, 2
3
4
6
16
15
addr
7
8
12
addr
10
data
14
data
11
13
17
18
19
R/W
PE2
20
21
22
LSTRB
PE3
23
24
25
NOACC
PE7
26
27
PIPO0
PIPO1, PE6,5
28
29
Figure A-1 General External Bus Timing
Freescale Semiconductor
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