MC9S12UF32 Datasheet, PDF (55/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
Internal Pull
Pin Name
Function
1
Pin Name
Function
2
Pin Name
Function
3
Pin Name
Function
4
Pin Name
Function
5
Supply
Rail
Resistor
CTRL
Reset
State
Description
Port A I/O pin; multiplexed
PA0
ADDR8/
DATA8
CFD8
ATAD8
SDCMD
VDDX
PUCR
Disabled
address/data; CFHC Data;
ATA5HC Data; SDHC SDCMD
signal.
PB[7:0]
ADDR[7:0]/
DATA[7:0]
CFD[7:0]
ATAD[7:0]
IOC[7:0]
VDDX
Port B I/O pin; multiplexed
PUCR Disabled address/data; CFHC Data;
ATA5HC Data; Timer channels
RESET
—
—
—
—
VDDR NA
NA External reset pin
BKGD
MODC
TAGHI
—
—
VDDR
Always
up
Up
Background debug; mode pin;
tag signal high
RPU
—
—
—
—
VDDA NA
NA
USB D+ pull up resistor
termination
RREF
—
—
—
—
VDDA NA
NA External bias resistor
DPF
—
—
—
—
VDDA NA
NA USB full speed D+ data line
DPH
—
—
—
—
VDDA NA
NA USB high speed D+ data line
DMF
—
—
—
—
VDDA NA
NA USB full speed D- data line
DMH
—
—
—
—
VDDA NA
NA USB high speed D- data line
3.3V regulator reference for
REF3V
—
—
—
—
VDDR NA
NA driving external NMOS regulator,
default output 0V
PJ0
SALE
CFIORW ATAIOWR
—
VDD3X
PERJ/
PPSJ
Port J I/O Pin; SMHC SALE
Disabled signal; CFHC IOWR signal;
ATA5HC IOWR signal.
PJ1
SCLE
CFCE1 ATACS0
—
VDD3X
PERJ/
PPSJ
Port J I/O Pin; SMHC SCLE
Disabled signal; CFHC CE1 signal;
ATA5HC CS0 signal.
PJ2²
SWP
CFCE2 ATACS1
—
VDD3X
PERJ/
PPSJ
Port J I/O Pin; SMHC SWP
Disabled signal; CFHC CE2 signal;
ATA5HC CS1 signal.
PM4
SBSY CFIOIS16 SDDATA2
IOC3
VDD3X
Port M I/O Pin; SMHC SBSY
PERM/
PPSM
Disabled
signal; SDHC data line; CFHC
CFIOIS16 signal; Timer
Channel.
PM3
SCE
CFINPACK SDDATA1
IOC2
VDD3X
Port M I/O Pin; SMHC SCE
PERM/
PPSM
Disabled
signal; SDHC data line; CFHC
CFINPACK signal, Timer
Channel.
PQ7
SDAT7
CFA7
IOC7
—
VDD3X
PERQ/
PPSQ
Disabled
Port Q I/O Pins; SMHC Data
line; CFHC address line; Timer
channel
PQ6
SDAT6
CFA6
IOC6
SDCLK
VDD3X
PERQ/
PPSQ
Disabled
Port Q I/O Pins; SMHC Data
line; CFHC address line; Timer
channel; SDHC Clock signal.
PQ5
SDAT5
CFA5
IOC5
SDCMD
VDD3X
Port Q I/O Pins; SMHC Data
PERQ/
PPSQ
Disabled
line; CFHC address line; Timer
channel; SDHC Command
signal.
Freescale Semiconductor
55