MC9S12UF32 Datasheet, PDF (3/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

Release
Number
Date
01.00 21AUG03
01.01 28NOV03
01.02 23MAR04
01.03 20APR04
01.04 10MAY04
01.05 03DEC04
Author
Y.H. Cheng
Wai-On Law
Y.H. Cheng
Wai-On Law
Wai-On Law
Wai-On Law
System on a Chip Guide — 9S12UF32DGV1/D V01.05
Summary of Changes
- Removed all references to XCLKS, since function is removed.
- typo - replaced PRU with RPU.
- typo - replaced ATAHC with ATA5HC
- Removed references to clock monitor, since function is not
available.
- Update θ_JA for 100-pin and 64-pin packages.
- Add footnotes on IRQ pin removal in 64-pin package
- Update Flash memory map out of reset.
- Add information on INITRM, INITRG, INITEE setting for example
application memory map
- Update clock distribution diagram to make it more intelligible
- Change table 2-3, 2-5 description using general purpose port
references instead of Functional module references.
- Stop IDD spec for -40C and 85C are removed
- Add other conditions for RUN Idd and Wait Idd.
- Minor typo corrections.
- Corrected ‘Background Debug Module’ to ‘HCS12 Breakpoint’ at
address $0028-$002F in table 1-1.
- Added detailed register map.
- Corrected the MSHC enable control in table 5-1.
- Added part ID $6311 for mask 1L47S.
- Removed all references and description on USB Physical
Endpoint 6
- Updated IDD, 3V and 5V I/O electricals and package thermal
resistance information
- Include Commercial tier note
- Update and add note to detailed register map.
- Added PIM reference.
- Added package information as appendix B.
- Improved fig 1-1.
- Fixed consistency of 3.0v and 3.3v for VDD3X.
- Updated power dissipation formula.
- Added schematic and PCB layout recommendations.
- Added NVM, VREGU, CRGU electricals to appendix A.
Freescale Semiconductor
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