MC9S12UF32 Datasheet, PDF (120/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
Table A-15 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, C_LOAD = 50pF
Num C
Rating
Symbol Min
Typ
Max
1 P Frequency of operation (E-clock)
f_o
0
30.0
2 P Cycle time
t_cyc
33
3 D Pulse width, E low
PW_EL
16
4 D _{Pulse width, E high}¹
PW_EH
16
5 D Address delay time
t_AD
5
6 D Address valid time to E rise (PW_EL–t_AD)
t_AV
11
7 D Muxed address hold time
t_MAH
2
8 D Address hold to data valid
t_AHDS
7
9 D Data hold to address
t_DHA
2
10 D Read data setup time
t_DSR
13
11 D Read data hold time
t_DHR
0
12 D Write data delay time
t_DDW
7
13 D Write data hold time
t_DHW
2
14 D Write data setup time⁽¹⁾ (PW_EH–t_DDW)
t_DSW
12
15 D Address access time⁽¹⁾ (t_cyc–t_AD–t_DSR)
t_ACCA
15
16 D E high access time⁽¹⁾ (PW_EH–t_DSR)
t_ACCE
3
17 D Read/write delay time
t_RWD
4
18 D Read/write valid time to E rise (PW_EL–t_RWD)
29 D Read/write hold time
t_RWV
12
t_RWH
2
20 D Low strobe delay time
t_LSD
4
21 D Low strobe valid time to E rise (PW_EL–t_LSD)
t_LSV
12
22 D Low strobe hold time
t_LSH
2
23 D NOACC strobe delay time
t_NOD
4
24 D NOACC valid time to E rise (PW_EL–t_NOD)
t_NOV
12
25 D NOACC hold time
t_NOH
2
26 D IPIPO[1:0] delay time
t_P0D
2
4
27 D IPIPO[1:0] valid time to E rise (PW_EL–t_P0D)
t_P0V
11
28 D IPIPO[1:0] delay time⁽¹⁾ (PW_EH-t_P1V)
t_P1D
2
25
29 D IPIPO[1:0] valid time to E fall
t_P1V
11
NOTES:
1. Affected by clock stretch: add N x t_cyc where N=0,1,2 or 3, depending on the number of clock stretches.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
120
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