MC9S12UF32 Datasheet, PDF (48/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
• USB 2.0 to CF bridge
Below table shows a summary of how the above configurations can be selected.
Table 2-2 Configuration selection in 64-pin option
Configuration
MODRR
ATA bridge
$03
Recommended IO
supply voltage
VDDX = 3.3V
VDD3X = 3.3V
Modules that can
be enabled
ATA5HC, SDHC
Modules that must
not be enabled
CFHC, SMHC, MSHC
Other Supporting
Modules that can
be enabled
SCI, TIM
SCI pins are routed to
PS[5:4]
SM, SD and MS bridge
$0F
VDDX = 3.3V
VDD3X = 3.3V
SMHC, SDHC and MSHC
ATA5HC, CFHC
CF bridge
$03
VDDX = 5.0V/3.3V
VDD3X = 5.0V/3.3V¹
CFHC,
ATA5HC, SMHC, SDHC,
MSHC
SCI, TIM
SCI, TIM
Specific Notes
General Notes
When TIMER is enabled,
timer channel pins IOC[7:5]
will be available on PQ[7:5];
IOC[3:2] are routed to
PM[4:3]; IOC[1:0] are
routed to PT[1:0]
SDHC pins are routed to
PQ[6:5], PM[4:3] and
PT[1:0]
When SDHC is enabled,
Timer channels IOC[6:5]
and IOC[3:0] pins will not
be available.
Appropriate external pull
up/down resistors required
on SDCMD, SDATA0 and
SDATA3.
SCI pins are routed to
PS[5:4]
Timer pins are routed to
PB[7:0].
SDHC pins routed to
PA[5:0]
SMHC pins routed to PA6
and PS[7:6]
Appropriate external pull
up/down resistors required
on MSBS, MSSCLK,
MSSDIO, SDCMD,
SDATA0, SDATA1, SDATA2
and SDATA3.
SCI pins are routed to
PS[5:4]
When TIMER is enabled,
timer channel pins IOC[7:4]
will be available on PQ[7:4]
if CA7E, CA6E, CA5E and
CA4E in CFSCR2 of CFHC
are set to 0.
Timer channels IOC[3:0]
are not available at pin
level.
If the pins are associated with a module which is not enabled, those pins can be
served as general purpose I/O at the voltage of the corresponding power supply rail.
NOTES:
1. VDDX and VDD3X should be at the same voltage as the CF card. Care should be taken when CFA3, CFA8, CFA9
and CFA10 are connected to CF card as they are supplied by VDDR with output swing of 0V to VDDR.
48
Freescale Semiconductor